Endian
A while after I started working on the Cortex-M3 product, I received an inquiry from a customer.”Is the Cortex-M3 a Little Indian or a Big Indian?”At first I thought it was Typo because this inquiry came via email. But I would not make a mistake in two places, and since the “i” and “e” on the keyboard are far apart, I thought I would not make a typo.Sure, the pronunciation is similar, but…I replied politely, “The Cortex-M3 is the (default) little endian.”It sounds like a made-up story, but it’s a true story.For more information on endians, please refer to the glossary of terms. This section explains the data format.
Cortex-M3 data format
As will be explained in detail in the chapter “Memory Map” (see Part 19), the Cortex-M3 memory is fixed address and linearly arranged.Cortex-M3 refers to its linear array of memory as a set of bytes, numbered in ascending order from 0.
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The Cortex-M3 endian is different in data and code.
- Data : accessible in Little Endian or Big Endian format
- Code : Always Little Endian
Little-endian is the default memory format for Arm processors, not limited to the Cortex-M3.Therefore, the byte with the lowest address in a word will be the lowest byte in that word.The byte with the highest address in the word is the topmost byte in that word.
In the Big Endian format, the byte with the lowest address in a word is the topmost byte in that word.The byte with the highest address in the word is the topmost byte in that word.
The figure below shows an example of a little-endian memory format and a big-endian memory format.
In Cortex-M3, the endian setting pin BIGEND (Note: It is not a microcontroller pin. (this is the name of the signal line to and from the outside of the logic module).This allows you to choose either the Little Endian or Big Endian format.The status of the BIGEND pin is reflected in the logic at the time of reset.Therefore, if you try to change the endian after a reset, you can’t.
（ * ）Access to the System Control Space (SCS) (see Glossary) is always little-endian.Whether the BIGEND function is effective or not depends on the microcontroller with Cortex-M3.Check the specifications of the microcontroller you are using.
Endian
The order in which numerical data of two bytes or more is handled is called endian.Big endian is the case where the upper digits are put into the memory in order.When you put it in order from the lower digits, it is called a little endian.For example, if we store 12 34 56 78h in memory, it looks like the following
System Control Space
This is the space in which the registers that control the Cortex-M3 system are located, starting with 0xE000E000.Specifically, the NVIC register, the SysTick register, the interrupt request enable set/clear/pending register, and the interrupt control state register are assigned.
memory format
Number of bits in a microcomputer
I’d like to ask you a few basic questions: what is a 32-bit microcomputer, and is it a 32-bit microcomputer if the CPU handles 32-bit data?Then, the CPU can perform 32-bit operations, but in the case of a microcomputer that has only a 16-bit bus connected to memory (ROM and RAM), is it a 16-bit microcomputer or a 32-bit microcomputer?Even if the arithmetic is 32 bits, if the data processing is only 16 bits, then it is only the processing power of a 16-bit microcomputer, but if the CPU is 32 bits, can we call it a 32-bit microcomputer?
Generally, the number of bits of data processed by the CPU is referred to as the number of bit microcomputers.However, there are no strict regulations. In reality, even though the CPU is 32 bits, there are microcomputers with a 16-bit memory bus that are called 32-bit microcomputers.
As mentioned above, CISC microcomputers do not have a fixed instruction code length, so even 8-bit and 16-bit microcomputers can have a 24-bit instruction length.RISC, on the other hand, has a constant instruction length in order to put it on the pipeline.Therefore, the processing capability of the microcomputer cannot be understood unless the data length and instruction length actually handled are properly checked without being influenced by the name of the number of bits of the microcomputer.
data type
Cortex-M3 data types
In the case of Cortex-M3, the instruction length is the Thumb-2 instruction set, so 32 bits and 16 bits are mixed.The data length can be 32 bits, 16 bits or 8 bits. Each data length is referred to as.
- 32-bit data : word
- 16-bit data : half word
- 8-bit data : Byte
As I mentioned in the chapter “Unaligned Data Access (see Part 8)”, the Cortex-M3 is a 32-bit microcontroller, so it is aligned every 32 bits.In other words, the unit of data accessed by the CPU is 32 bits.When storing 8 or 16 bits of data in memory, we don’t store data across 32 bits of alignment (boundaries) unless we use unaligned data access.
The user (and by extension, the compiler’s memory system) needs to be careful when dealing with all the data lengths.Care must be taken to avoid corrupting data of different lengths next to each other, especially when dealing with word, half-word, and byte data next to each other.
Exception/interrupt handling
What is exception handling?
Exception handling is a process in which a microcontroller is suddenly required to perform another task when it is executing the main routine.In many cases, this refers to interrupts, but resets also go into respectable exception handling, as they suddenly stop and initialize the main routine.In addition, in Cortex-M3, when an abnormal situation occurs while executing the main routine and the main routine cannot be executed, a process called “fault” is performed.This is also one of the exceptions, as you will suddenly have another job to do.From the MCU’s point of view, exception handling occurs at an unexpected timing, so the transition timing is quite difficult to handle.How quickly and efficiently an exception is executed and returned to the main routine is a key point in the design of each microcontroller.
If all exception handling is done by software, the cost can be kept down because the hardware burden is small, but the processing time is long and slow.It also requires a lot of Flash to write programs for the process. (The microcomputer is cheap, but it adds to the user’s effort and Flash capacity.)If you leave everything to the hardware, the software burden is reduced and the Flash capacity is reduced, but the logical scale is increased and there is a disadvantage in terms of cost. (The microcontroller will be more expensive, but the user’s effort and Flash capacity will be reduced.)At the stage of specification study, including the cost of microcomputers, it is important to decide how much to leave to the software and how much to the hardware.How much hardware and software should be shared is a concern for each microcomputer designer.
As a matter of fact, it is not possible to handle all exceptions with software.Hardware is needed to manage priority when exceptions are raised, and to jump to vectors, etc.For this reason, a normal microcontroller has more or less hardware built in to handle interrupts.In general, microcomputers with only the minimum required interrupt hardware are often not shown in the block diagram (e.g., Arm7, see the figure below).If it has hardware that can handle advanced interrupts, that hardware is also a selling point, so it may be mentioned, for example, “Equipped with an interrupt controller.
The extent to which this interrupt controller is responsible for the work varies depending on the microcontroller.For example, there is a method of writing jump instructions (or exception-only instructions) in an interrupt vector, and when an exception occurs, the CPU executes the instructions in that vector.Also, there is a method to write the jump destination address in the vector and make the hardware jump automatically (in the case of Cortex-M3), etc.The detailed specifications for exception handling are different for each microcontroller.
Nested Vectored Interrupt Controller(NVIC)
The figure below shows a block of conventional Arm7 and Cortex-M3 cores, with the red circled part of Cortex-M3 being the NVIC.The Arm7 core does not have the sophisticated hardware to control such interrupts.As mentioned in the chapter “Overview of the Cortex-M3 Processor” (see Part 3), the Cortex-M3 has an NVIC, which is closely related to the processor core so that exception handling, such as interrupts, can be handled efficiently.
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The state transition diagram of the Arm7 exception handling is shown in (a) below, and the Cortex-M3 case is shown in (b).In the case of Arm7, there are more “vector table” states than in the case of Cortex-M3 because of the software intervening parts.
Arm7 state transitions
In Arm7, when an interrupt occurs, the
- Jump to Vector Table
The hardware does this, but the software does the work of storing the context of the microcontroller on the stack.in other words - Register Retreat
- Jump to handler processing
These processes are performed by the software. The exception handling code will then be executed in handler mode. - exception handling
Once the exception handling is complete, the process of returning to the main routine begins. - Register Restoration
after that - execution of a return instruction
The hardware starts working again - Jump to the return address
It is a series of actions from “1” to “7”, and “2” to “6” must be performed by software.
Cortex-M3 state transition
In the case of Cortex-M3, when an interrupt occurs, the
- Automatic saving of general-purpose registers
- Jump to Vector Table
- Jump to handler processing
Since the hardware does all of these actions, the software doesn’t have to do anything until it goes into handler mode. - exception handling
When the exception handling code has been executed, return to the main program. - execution of a return instruction
Then, the hardware is again - General Purpose Register Recovery
- Jump to the return address
Since these processes are performed, there is no need for software to perform push, POP, etc. processes.If only “4” and “5” are done by software in the series of operations from “1” to “7”, all other processes are done by hardware, which makes it very easy for the user.In addition, hardware allows each process to be executed efficiently, thus reducing the overhead of state transitions.
Exception Handling Language
In Arm7, the software was required to move to and back from interrupt handling. This point is very inconvenient for the user.In addition, the language in which it was processed had to use an assembler language.
AIn RM7, as shown in the figure below, the The main routines could be written in C, but the exception handling code had to be written in assembler.And since there are also two instruction sets, Arm and Thumb, Linker had to link these four languages (instruction sets).However, with Cortex-M3, the NVIC allows handlers to handle the processing that Arm7 did in assembly language software, allowing for interrupt processing that can be written only in C.In addition, the instruction set has been unified to the Thumb-2 instruction set, so as you can see on the right side of the figure below, the linker processing in Cortex-M3 is much simpler than in Arm7 on the left.In addition, the hardware handlers are now able to handle interrupts with short overhead.
Main Features of NVIC
The following is a list of NVIC features
- External interrupts can be set to a value between 0 and 239.The external interrupt here is not an external interrupt of the microcontroller, but an external interrupt as seen from the Cortex-M3.Therefore, it refers to the microcontroller’s peripheral functions (timers, communication modules, analog modules such as ADCs, etc.).
- The interrupt priority is set by dividing the 8-bit registers into two groups.In actual products, it is not necessary to use the full 8-bit register, and the number of bits used can be selected by the microcontroller manufacturer.(Can be set between 3 and 8 bits.)
- The priority of the interrupt can be dynamically changed (re-set).
- In the Cortex-M3 manual, you may see the words “Tail-Chaining” and “Late Arrival” in the description of interrupts.More on this later, but these are Arm-specific words (concepts).By incorporating Arm-specific concepts, we have achieved very short overhead interrupt handling when storing and restoring context in transitions between two or more successive interrupts.
- When an interrupt occurs, the handler (hardware) saves the context and restores it when it returns from the interrupt, so there is no instruction overhead.
- Long instructions such as LDM (load), STM (store), and division can be interrupted, and when an interrupt occurs, it can be paused, given priority to the interrupt process, and then rerun after the process is complete.
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