目次
Cash Policy
Write-through policy
A write access that hits the data cache will write data to the cache RAM. If the memory area is marked Write-Through, then the write operation is also performed on the AXIM interface and the same data is stored in external memory to ensure that the external memory and cache are consistent. If there is a secondary cache (L2 cache) between the L2 cache and the external memory, the data is stored in the same way. Then, the effective bit V in the L1 cache becomes effective.
Write-back policy
If the memory area is write-back, then valid bit V and dirty bit D in the L1 cache are enabled and the cache lines are marked as dirty. Writes are performed in AXI only in the case of eviction. When a dirty cache line is evicted, the data is written through a write buffer in the AXIM interface that writes to the external memory system.
Default memory mappings and attributes
Default Attributes
As mentioned above, the memory attributes are set by default for each memory area as shown in the table below.
| Address | Name | Memory Type | XN | Cache | Description |
|---|---|---|---|---|---|
| 0x0000 0000～0x1FFF FFFF | Code | Normal | – | WT | Typically, ROM or Flash memory. Memory required from address 0x0 to support a vector table for system code in resets. |
| 0x2000 0000～0x3FFF FFFF | SRAM | Normal | – | WBWA | SRAM area. Generally, it is used for internal RAM. |
| 0x4000 0000～0x5FFF FFFF | Peripheral | Device | XN | – | built-in peripheral function address space |
| 0x6000 0000～0x7FFF FFFF | RAM | Normal | – | WBWA | Write-back memory, write allocation and cache attributes with L2/L3 cache support |
| 0x8000 0000～0x9FFF FFFF | RAM | Normal | – | WT | memory for write-through cache attribute |
| 0xA000 0000～0xBFFF FFFF | Device | Device、Shareable | XN | – | shared device space |
| 0xC000 0000～0xDFFF FFFF | Device | Device、Non-shareable | XN | – | Unshared device space |
| 0xE000 0000～0xE00F FFFF | PPB | Strongly-Ordered | XN | – | 1MB of space is reserved for PPB. This supports key resources (including system control and debug areas). |
| 0xE010 0000～0xFFFF FFFF | Vendor_SYS | Device | XN | – | Vendor System Area |
MPU（MPU_RASR：MPU Region Attribute and Size Register）
You can use MPU (MPU_RASR: MPU Region Attribute and Size Register) to change the memory attribute defaults.
Line Fill and Eviction Buffer
As mentioned in the AXI interface chapter, there is one line fill buffer for instructions, two line fill buffers for data, and one write buffer, each 32 bytes.
Data line fill buffer
- Used for load start and store initiated line fills.
- Store from store buffer can be merged into line fill buffer.
- This is used for non-cached read bursts.
That is, for write back, the write allocate when the data cache misses will store the data that the data cache missed. The line fuels start using one of the two line fill buffers. When the line fill data is returned from the external memory system, the data in the store buffer is merged with the line fill buffer and then written to the cache.
write buffer
- It’s used for eviction.
- It is used for write-through, read-allocation and non-cached write bursts.
Overview of ECC (Error Correcting Code)
ECC
The Cortex-M7’s cache has an ECC, which allows you to check in the cache RAM with the ECC. It can then recover/disable/retry any errors detected in the cache RAM. When an error is detected, the corresponding index/way is cleaned and disabled, as shown in the table below. Once cleaned and disabled, the requestor will retry the access. ECC can also be used to correct single-bit errors in RAM.
Error Correcting Code (ECC) is an option for microcontroller manufacturers, so it is dependent on the individual product specifications. Be sure to check the manual of the product as some products may not actually have ECC.
If the cache has ECC built in and enabled, it is combined with individual lines of tags. Whenever a lookup is performed in the cache, the data read from the cache is checked, and if the data is correctable, it is checked before the processor uses the data. And if the data is correctable, it is corrected before the processor uses the data.
instruction cache
The line is sufficiently disabled so that the line is always clean. When access is retrying, the correct value is fetched from external memory.
data cache
The data cache allows you to dirty the cache lines. Corrections to the contents of the cache RAM are performed as part of the clean and deactivate operations for the cache. This happens in the write buffer and the corrected data is written back to external memory. When the access is retried, the correct value is read out of external memory. If the data cannot be corrected at that time, then the error could not be recovered.
| RAM type | Protection | Recoverable errors | Unrecoverable Error | Hard Error Support | |
|---|---|---|---|---|---|
| data | Tag RAM | SEC-DED ECC | Error deemed to be a single-bit error | Error deemed to be multiple bit error | Up to two hard errors. |
| Cached Data RAM | SEC-DED ECC | Error deemed to be a single-bit error | Errors that are considered multi-bit errors on the dirty line | ||
| order | Tag RAM | SEC-DED ECC | Tags stored in RAM or valid single- or double-bit errors | None(*) | |
| Cached Data RAM | SEC-DED ECC | Error on data stored in RAM | None(*) | ||
(*) The instruction cache is never dirty because cache RAM errors are always recoverable by disabling the cache and trying the instruction again.
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