AXI transfer

AXI transfer limitations

The following restrictions apply when performing AXI transfers.

• Burst is up to 32 bytes
• Burst length up to 4 transfers
• The maximum length of a write burst in Strongly-ordered memory or Device memory is 2 transfers
• A read of Strongly-ordered or Device memory is always a single transfer
• No transaction crosses a 32-byte boundary of memory. The processor splits an AXI burst when accessing an address that spans a 32-byte boundary, the boundary of a cache line; instructions that access memory across one or two 32-byte boundaries produce two or three AXI bursts, respectively
• No fixed bursts are used
• The write address channel is always an incremental type burst, never wrapping (when the address reaches the end of memory, it continues to access the beginning of memory back to the beginning of memory) or fixed
• Wrapping type memory is

  – Used to line fill (read) cacheable Normal memory

  -Always 4 transfers in 64 bit size

  -Always a 64-bit boundary start address

  (Reference) When a load and instruction fetch from Normal cacheable memory hits the cache and the corresponding cache is running, a cache line fill occurs. The values of ARADDRM, ARBURSTM, ARSIZEM and ARLENM for cache line fills are shown in the table below

• For an 8-bit 16-bit size transfer, the burst length is always one transfer
• Since it is a 64-bit AXI, the transfer size is no larger than 64 bits
• The instruction fetch is always a 64-bit transfer size, and is never locked or exclusive
• Transactions to Device and Strongly-ordered memory are always made to addresses aligned with the transfer size. Accesses to device memory or Strongly-ordered memory using LDM, STM, LDRD, and STRD instructions are all performed as 32-bit transfers.
• Exclusive access is always to addresses aligned with the size of the transfer
• Only exclusive access to shared memory will result in exclusive access on AXIM

Data Cache

AXI transactions when there is a data cache

An AXI transaction can be created when there is a data cache and

Normal, cache-enabled memory

• Wrapping 4 (WRAP4) for 64 bit read, load and write back and write allocation of store and instruction line fills to line fills
• Increment 4 (INCR4) for 64-bit writing and eviction
• Increment N (INCR N) (1-4) for 64-bit write transfers, coordinated individual write-through or write-back, or no write-allocation store
• Increment N (INCR N) (1-4) for 64-bit read transfers, for loading when the data cache is disabled, or for instruction fetching when the instruction cache is disabled

Normal, non-cacheable memory

• Increment N (INCR N) (1-4) 64 bit write transfer, for individual stores and multiple stores
• Increment N (INCR N) (1-4) for 64-bit read transfers, individual loads and multiple loads
• Increment N (INCR N) (1-4) for 64-bit read transfer and instruction fetching
• Increment 1 (INCR 1) for 8-bit and 16-bit and 32-bit, exclusive read and write, shared exclusives

Strongly Ordered Memory or Device

• Increment 1 (INCR 1) for 8 and 16 bits and 32 bits, read and write, individual load and store
• Increment 1 (INCR 1) for 32-bit, read/write transfer, multiple loads
• Increment N (INCR N) (1-2) 32 bits, write transfer, for multi-stores
• Increment 1 (INCR 1) 8 and 16 bits and 32 bits, for exclusive read and write, shared exclusives

Fixed bursts are not used

Bursts written to Normal memory can use the following optimizations

• Whole beat without strobe set
• Non-continuous strobes per beat

These are allowed on the AXI in which the AHB bridge is implemented.

AXI transactions in the absence of data cache

AXI transactions can be created in the following cases when there is no data cache

Normal memory

• Wrapping 4 (WRAP4) 64 bit readout, instruction line fill with instruction cache
• Increment N (INCR N) (1-4) for 64-bit read/write transfers, individual loads and multiple loads
• Increment N (INCR N) (1-4) 64 bit write transfer, for individual stores and multiple stores
• Increment N (INCR N) (1-4) for 64-bit read transfers, for non-cached instruction fetching, or for fetching all instructions when there is no instruction cache
• Increment 1 (INCR 1) for 8-bit and 16-bit and 32-bit, exclusive read and write, shared exclusives

Strongly Ordered Memory

• Increment N (INCR N) (1-2) 32 bit write transfer, for individual stores and multiple stores
• Increment N (INCR N) (1-2) for 32-bit read/write transfers, individual loads and multiple loads
• Increment 1 (INCR 1) 8-bit/16-bit/32-bit, for exclusive read and write, shared exclusives

Fixed bursts are not used

Bursts written to Normal memory can use the following optimizations

• Whole beat without strobe set
• Non-continuous strobes per beat

These are allowed on the AXI in which the AHB bridge is implemented.

ID

The following ID reads and writes are available on the AXI.

Read ID

• ID0 – Single Normal Uncacheable Memory and Device and Strongly Ordered Memory Read
• ID1 – Data cache line fill from line fill buffer 0
• ID2 – Data cache line fill from line fill buffer 1
• ID3 – Instruction Fetch

Writing ID

• ID0 – Normal Uncacheable Memory and Exclusive Store Transfer
• ID1 – Normal cacheable write-through, write-back, no write-allocation to memory
• ID2 – Write to Device or Strongly-ordered memory
• ID3 – Eviction to Normal Cacheable Write-back Memory

投稿者

菅井 賢

国内外の半導体メーカーにおいて、マイコンの設計・開発・技術サポートに従事。2019年インスケイプ株式会社へ入社。APS初心者講座「Cortex-M編」の執筆をはじめ、豊富な経験と知識を活かし、初心者にもわかりやすい技術記事を提供している。

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