Power Management, Core Debugging, Floating Point Unit

Power Management
Core Debugging
Floating point unit

Power Management

Multiple sleep modes

The Cortex-M7 also supports the same low power mode as the Cortex-M3/M4. The basics are the same as the Cortex-M3/M4; the Cortex-M7 has three different sleeps if you include the WIC (Wake Up Interrupt Controller).

Sleep mode
Deep sleep mode (no WIC)
Deep sleep mode (with WIC)

For more information on each mode, transition conditions, and wake-up procedures, see “Cortex-M, Part 20”.

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2014.03.30

WIC

WIC is a vendor option, so some products may not have it. It is a feature that Cortex-M3 and M4 also have, but it is included in Cortex-M3 revision 2 (r2p0) and later, so the early Cortex-M3-based microcontrollers do not have it.

The WIC can detect interrupts and wake the processor up from deep sleep mode; to enable the WIC, set the DEEPSLEEP bit in the SCR register to 1. The WIC is not programmable, so the register or user interface is not I don’t have one. It operates entirely on hardware signals.

When WIC is enabled and the Cortex-M7 goes into deep sleep mode, the power management unit in the system will power down the majority of the Cortex-M7 processor. It is important to note that the system timer (SysTick) will also stop at that time.

When the WIC receives an interrupt, it wakes up the processor before processing the interrupt. At that time, the number of clock cycles is required for the state restoration process. This means that the delay time for interrupt processing increases in deep sleep mode. The processor disables the WIC when it detects a connection to the debugger.

How to enter low power consumption mode

(1) WFI (Wait for interrupt)

WFI (Wait for interrupts instruction) causes an immediate entry to sleep mode.

(2) Wait for event (WFE)

WFE (event waiting instruction), depending on the value of the 1-bit event register, causes an entry into sleep mode. When the processor executes the WFE, it checks the value of the event register.

0: The processor stops executing instructions and enters sleep mode.

1: The processor clears the register to 0 and continues to execute the instruction without going into sleep mode.

If the event register is 1, this indicates that the processor does not enter sleep mode with the execution of the WFE instruction. This is because an external event signal (if implemented) has been asserted or the processor in the system has executed a SEV instruction. The software cannot directly access this register.

③SLEEP on EXIT

If the SLEEPONEXIT bit in the SCR register is set to 1, the processor will return to threaded mode (See Cortex-M, Part 8) and immediately enters sleep mode.
This mechanism is very useful for applications that use only one exception and want to automatically enter sleep mode when the exception ends.

Recovery from Low Power Mode

(1) Recovery from Low Power Mode and SLEEP on EXIT using WFI

Normally, the processor will only get up from low-power mode if it detects an exception of sufficient priority to trigger exception handling. In some embedded systems, after the processor has risen, the system may have to perform a restore run of the task before executing the interrupt handler.

To do this, set the PRIMASK bit to 1 and set the FAULTMASK bit to 0. If a valid interrupt occurs and has a priority higher than the current exception’s priority, the processor gets up, but does not execute the interrupt handler until the processor sets the PRIMASK bit to 0.

(2) Recovery from low power consumption mode by WFE

The processor will rise from low-power mode when the following events occur

When an exception of sufficient priority to cause an exception entry is detected
When an external event signal is detected, if an optional external event input is implemented
In a multiprocessor system, when another processor in the system executes a SEV instruction

On the other hand, if the SEVONPEND bit in the SCR register is set to 1, some new pending interrupts will trigger an event and wake up the processor, even if the interrupt is disabled or in a priority order that is not sufficient to cause an exception entry.

Core Debugging

Debugging functions of Cortex-M7

The debugging capabilities of the Cortex-M7 have processor Halt, single step, processor core register access, vector catch, infinite software breakpoints, and full system memory access. The processor also includes support for hardware breakpoints and watchpoints set during implementation.

Breakpoint units that support 4-8 instruction comparators
Watchpoint units that support 2 or 4 watchpoints

For processors that perform debugging, Arm recommends that the debugger identify and connect to the CoreSight (See Cortex-M, Part 3) debug infrastructure to connect to the debug components.

The figure below shows the recommended flow that the debugger follows to find the component in the CoreSight debug infrastructure. In this case, the debugger reads the component ID registers for the peripheral devices and the individual CoreSight components in the CoreSight system.

Debugger Cortex-M7 identification

To identify the Cortex-M7 processor in a CoreSight system, Arm recommends that the debugger perform the following

Identify and place the Cortex-M7 processor ROM table using the CoreSight ID.
Follow the pointers in the Cortex-M7 processor ROM table to PPB ROM table.

a. System Control Space (SCS).

b. Breakpoint unit (FPB: Breakpoint unit).
– Number of BKPT comparisons – 4 or 8
– Match with instruction fetch

c. Data Watch point and Trace unit (DWT).
– Number of DWT comparisons – 2 or 4
– Data access and PC and data values and cycle counts

d. Instrumentation Trace Macrocell Unit (ITM).
– Supports “printf-style” for software-controlled tracing

Floating point unit

Overview

The Cortex-M series floating point unit was the first Cortex-M4 to have an FPv4 architecture, FPv4 only allowed for single precision arithmetic, but the Cortex-M7 has been updated to FPv5, which also allows for double precision arithmetic. Several additional instructions have been added for double precision arithmetic, using the same load/store instructions, since the FPv4 expansion already allowed support for 64-bit data.

This is an option for the microcontroller vendor, so check the product’s manual to see if it’s included. Some products have it, but only for single precision operations, so be careful.

Integrated hardware floating point (optional for microcontroller vendors)

FPv5 Architecture
16 64-bit double-word registers: D0 to D15
32 32-bit single-word registers: S0 to S31
ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic compliance

Operations are performed in hardware

Multiplication, addition, subtraction, and sum-of-products operations
Comparison, format conversion (fixed-point to floating-point)
Division, square root

Disable immediately after reset

Needs to be enabled and configured in the software

Compatibility with ANSI/IEEE Std 754-2008

Without using the default NaN (DN) and Flush-to-Zero (FZ) mode, the FPv5 function complies with the IEEE 754 standard on hardware, so no support code is required.

Flush-to-zero mode: replace the number of denormalizations with 0
Default NaN mode: default NaN is returned by all operations whose input is NaN (non-numeric) or whose result is NaN

Enabling FPU

Since the FPU is disabled immediately after resetting, the user must enable the FPU before using an immovable instruction. The following is sample code to initialize the FPU in privileged mode (supervisor mode). The processor must be in privileged mode to read/write the CPACR registers.

CPACR EQU 0xE000ED88

　　LDR R0, =CPACR ; Read CPACR
　　LDR r1, [R0] ; Set bits 20-23 to enable CP10 and CP11 coprocessors
　　ORR R1, R1, #(0xF « 20)
　　STR R1, [R0] ; Write back the modified value　to the CPACR

　　DSB
　　ISB ; Reset pipeline now the FPU is enabled.

Three fields

Sign
Biased exponent (sum of the exponent plus a constant bias value)
Magnitude

Single-precision: 32-bit code length

Double-precision: 64-bit code length

Semi-precision: 16-bit code length

Normalized Floating Point Number

normalized floating point number
The numbers are coded as follows: code + fixed-point value (1.0~2.0) x 2N
Sign section (1 bit)
0: Positive
1: Negative
Single-precision index section (8 bits)
Index range: 1 – 254 (0 and 255 are reserved)
Bias: 127
Exponent – Bias value range:-126 ~ +127
Single-precision mantissa section (23 bits)
Mantissa: A number between 0 and 1: ∑(N_i.2^-i) (i = 1 to 24 range) 23-bit Ni value is stored in the mantissa part.
(-1)^s x (1 + ∑(N_i.2^-i) ) x 2 ^{(Exponent – Bias)}

Floating point rounding

closest rounding
Default rounding
In the case of a value between two proximity values, adopt a value where the mantissa LSB is zero.
directional rounding
Three user-selectable directional rounding modes
+∞, -∞ or rounding to near zero.

floating point arithmetic

Addition, subtraction, multiplication, division, remainder, and square root

Floating point format conversion

Floating point to integer, rounded floating point to integer value, binary to decimal conversion, and comparison.

Exception handling

Invalid operations: the result is NaN (non-numeric)
Divide by 0
Overflow: depending on rounding, if the value written to the destination register exceeds the infinity value of +/- or the maximum value of +/-
Underflow: When a denormalized number is written to the destination register
Incorrect results: results caused by rounding