register

Core Register Set
Registers from the programmer’s point of view
Registers and Operation Mode
Floating point and NEON register

Core Register Set

All Arm processors use a load/store architecture, where arithmetic is done in registers. An instruction has access to all 16 registers, but r13 to r15 have a special role.

stack-pointer
Holds the address of the memory area used to temporarily save the current register value.
link register
Stores the address of the next instruction of the BL instruction and the return address for the function call.
program counter
Holds the address where the program is running; for Thumb-2 instructions, instructions are placed in word or half-word increments and bit 0 is undefined.

cpsr (current program status register)

It holds the processor’s operation results and the status of the operation mode and interrupt settings, and is used for program control and other purposes.

【cpsr format】

Name	meaning
N	This is set if the result is negative.
Z	This is set if the result is zero.
C	This is set if the result of the calculation is a carryout.
V	This is set if the result of the operation is an overflow.
Q	Indicates that saturation has occurred. (Not auto-cleared)
J	Indicates that saturation has occurred. (Not auto-cleared)
GE[3:0]	This is used in some SIMD instructions.
IT[7:0]	This is used in the IF-THEN conditional execution of the Thumb2- instruction.
E	Sets the endian format of the load/store instruction.
A	Prohibits inaccurate data aborts.
I	Setting IRQ interrupt. (I=1: IRQ interrupt disabled)
F	Setting the FIQ interrupt. (F=1: FIQ interrupt disabled)
T	T=0: processor is state/T=1: processor is THUMB state
MODE[4:0]	Sets the processor operating mode.

Registers from the programmer’s point of view

To write programs efficiently, you need to consider the arguments and return values to the functions used by the C/C++ compiler. The specification of arguments and return values to functions is described in the “AAPCS ( (Procedure Call Standard for Arm Architecture) “.

Programming with AAPCS in mind

Arm processors can use 64-bit data. In that case, performance can be improved by swapping the order of function argument definitions: 64-bit arguments are passed using even-numbered registers and contiguous odd-numbered registers, and the stack must be aligned to 8 bytes. Also, the stack must be aligned to 8 bytes.

Basics of function calls

If you have up to four 32-bit arguments, you can pass arguments in registers, which allows you to make function calls more efficiently.

if long long type is included

The variable b is a 64-bit argument.

Containing double type

Registers and Operation Mode

The Cortex-A processor has certain registers that automatically switch depending on the mode of operation (see Part 5), certain registers are automatically switched depending on the mode of operation (see Part 2), increasing the number of registers available and speeding up operation without changing the instruction set architecture.

Floating point and NEON register

The Cortex-A processor can be optionally equipped with Arm Floating Point Architecture (“VFP”) and simultaneously equipped with the NEON General Purpose SIMD Engine (“NEON”). The version of VFP that can be installed varies by processor.

Processor Series	VFP type
Cortex-A5	VFPv4
Cortex-A7	VFPv4
Cortex-A8	VFPv3
Cortex-A9	VFPv3-D16
Cortex-A12	VFPv4
Cortex-A15	VFPv4

The VFP and NEON registers share some registers and use a different set of registers than the core registers (r0-r15).

The s register is 32 bits, the d register is 64 bits, and the q register is 128 bits. It is also possible to use the same register in different sizes.

投稿者

APS

毎月約50,000人のエンジニアが利用する「APS-WEB」の運営、エンジニア限定セミナー「APS SUMMIT」の主催、最新事例をまとめた「APSマガジン」の発行、広い知識と高い技術力を習得できる「APSワークショップ」の開催など、半導体専門技術コンテンツ・メディアとして日々新しい技術ノウハウを発信しています。