Vector table, exception

Vector table
Exceptions

Vector table

What is a vector table

A vector table is a table that stores instructions and addresses for executing a program that starts processing when an exception is raised (generally called an “exception handler”).

What is an Arm processor vector table

The Arm processor’s vector table is located at 0x00000000, but can be moved to the upper vector address (0xFFFF0000) by the V-bit (bit 13) of the CP15 System Control Register or the VINITHI pin. If a security extension is in place and no upper vector address is selected, the vector address can be changed with the Vector Base Address Register (VBAR).

Although a branch instruction for the Arm instruction (32-bit) is written in the vector table, the FIQ interrupt is placed at the last address in the vector table, allowing interrupt handlers to be written directly without using a branch instruction.

Many dedicated registers are available for FIQ interrupts, which shorten the time required to return to the stack for interrupt processing, thus enabling fast processing. For the register set, please refer to “Part 4: Registers“.

Normal Vector Offset	Higher Vector Addresses	Exceptional Factors
0x00	0xFFFF0000	Reset
0x04	0xFFFF0004	An undefined instruction exception
0x08	0xFFFF0008	Supervisor Call (SVC)
0x0C	0xFFFF000C	Pre-fetch Abort
0x10	0xFFFF0010	Data Abort
0x14	0xFFFF0014	Booking
0x18	0xFFFF0018	IRQ interrupt
0x1C	0xFFFF001C	FIQ Interrupt
	….

How to write a vector table

There are two ways to create an interrupt vector table: using the LDR (literal pool) instruction or using the B instruction (PC relative branch instruction) The B instruction can be executed faster than the LDR instruction by writing exception handlers within a range of ±32 Mbytes. [LDR instruction (literal pool)]

【Vector table with LDR instructions (literal pool)】

    PRESERVE8                           ; 8バイト境界で境界調整されたスタックを保持
    AREA VECTORS,CODE,READONLY          ; VECTORS領域としてセクションを定義

Vectors_Table
    LDR   PC,Reset_Addr                 ; リセット例外
    LDR   PC,Undefined_Addr             ; 未定義命令例外
    LDR   PC,SVC_Addr                   ; ソフトウェア割り込み
    LDR   PC,Prefetch_Addr              ; プリフェッチアボート例外
    LDR   PC,Abort_Addr                 ; データアボート例外
    B   .                               ; 予約ベクタテーブル
    LDR   PC,IRQ_Addr                   ; IRQ割り込み
    LDR   PC,FIQ_Addr                   ; FIQ割り込み
;
; 実行開始処理アドレス定義
;

Reset_Addr DCD Reset_Handler
                                ; exception handler first address definition
Undefined_Addr DCD Undefined_Handler
                                ; Undefined instruction exception handler top address definition
SVC_Addr DCD SVC_Handler
                                ; software interrupt handler first address definition
Prefetch_Addr DCD Prefetch_Handler        
                                ; Prefetch abort exception handler top address definition
Abort_Addr DCD Abort_Handler
                                ; Data abort exception handler first address definition
IRQ_Addr DCD IRQ_Handler
                                ; IRQ interrupt handler first address definition
FIQ_Addr DCD FIQ_Handler
                                ; FIQ interrupt handler top address definition

【Vector table using the B instruction (PC relative branch instruction)】

    PRESERVE8; keeps the stack bounded on 8 byte boundaries
    AREA VECTORS,CODE,READONLY ; define a section as a VECTORS area

Vectors_Table
    B Reset_Handler ; Reset exception handler
    B Undefined_Handler ; Undefined instruction exception handler
    B SVC_Handler ; software interrupt handler
    B Prefetch_Handler ; Prefetch abort exception handler
    B Abort_Handler ; data abort exception handler
    B .                       ; Reserved vector table
    B IRQ_Handler ; IRQ interrupt
    B FIQ_Handler ; FIQ Interrupt

How to arrange the vector table

The target memory allocation settings (ROM/RAM, etc.) are set up by a method called scatter loading in the case of Arm compiler. Set the assembly source file “vector.s” which describes the vectors as the section name “VECTORS”. For details, please refer toArm Compiler armlink User Guide.

【Example of a scatter loading file】

LOAD 0x00000000 0x20000000 ; placed in 256Mbyte memory
{ 
    VECTORS 0x00000000
    {
        vector.o(VECTORS,+FIRST) ; Vector table is placed from the beginning 0x00000000
        *(+RO) ; Place another object
    }
...
...
}

In the scatter loading file, set the vector table to the FIRST attribute and place the VECTORS section at the beginning of the image. With this setup, the vector table is placed from 0x00000000. Other objects are placed according to the linker placement rules.

Exceptions

Processor behavior when an exception occurs

When an exception occurs, after the assembler instruction of the execution is finished, the cpsr (current program status register) is saved in the spsr (saved program status register) of the corresponding mode and the return address is saved in r14 of the corresponding mode.
Change the processor mode and prohibit exceptions depending on the source of the exception.
Call the exception handler according to the instructions in the vector table.
If necessary, save the registers to the stack.
Execute an exception handler.
Returns the registers saved to the stack.
Returns according to the cause of the exception.

What is the priority of exceptions

Exceptions have a priority level, and if more than one exception occurs simultaneously, they are handled according to the priority level. Reset exceptions have the highest priority and can be executed in any situation.

Exceptional factors and mode of operation

The IRQ/FIQ interrupt can be disabled/allowed, but no other exceptions can be made, and the Arm compiler has a built-in function for IRQ/FIQ interrupt control that allows the C/C ++ languages.

Exception factors	Operation mode	Occurrence factors	No Exceptions
Exception factors	Operation mode	Occurrence factors	FIQ	IRQ
Reset Exceptions	Supervisor	Execute a reset exception after the reset input. Reset exceptions are the highest priority exceptions and do not allow exception prohibitions to be enforced.	×	×
Undefined instruction exceptions Undefined	Occurs when you execute an undefined instruction.	—	×
SVC (Supervisor Call)	Supervisor	Occurs when the SVC instruction is executed.	—	×
Pre-fetch Abort	Abort	Occurs when executing an instruction fetch from an invalid address.	—	×
Data Abort	Abort	Occurs when performing a read/write of data from an invalid address.	—	×
IRQ interrupt	IRQ	This occurs when an IRQ is entered.	—	×
FIQ Interrupt	IRQ	This occurs when an IRQ is entered.	×	×

Operation of register set in case of exception operation

This section describes the behavior of the register set when IRQ interrupt is generated.

r13 and r14 switches to IRQ interrupts only.
cpsr will be stored in spsr for IRQ mode.
RQ interrupts will be disabled.

How to recover from an exception

If an exception is raised, the link register in the operating mode is returned and addressed according to the exception factor. When returning from an exception, the link register r14 must be corrected according to the exception factor that has been raised.

【List of link register correction values】

Exceptional Factors	corrected value	Return to
SVC	0	次の命令
An undefined instruction exception	0	Next Instruction
Pre-fetch Abort	-4	The instruction that generated the abort
Data Abort	-8	The instruction that generated the abort (if it is an exact abort)
FIQ Interrupt	-4	Next Instruction
IRQ interrupt	-4	Next Instruction

To perform an exception recovery, the following actions must be performed atomically (*1).

Correct the link register r14 as necessary and copy the program counter r15.

Copy from spsr to cpsr.

(*1) Atomic means that when multiple operations are combined, they become one operation in terms of the rest of the system.

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