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Exceptions and interruptions

投稿日 2014年9月20日 APS 0

　

Exceptions

The difference between exceptions and interrupts

An exception is a process in which a program is in the middle of executing a certain process and is suddenly required to perform a different task (task). General-purpose exceptions that have no defined purpose are called interrupts, and Arm processors (except for the Cortex-M series) can use IRQs/FIQs as interrupts.

This section describes the exceptions that occur in the Cortex-A series, including what causes them and how they are controlled.

Reset Exception

All processors have a reset input and execute a reset exception immediately after a reset. Reset is the highest priority exception and cannot be prohibited.

Undefined Instruction Exception

An undefined instruction exception is raised in the following cases

  • If the core attempts to execute the opcode with a truly undefined instruction
  • If the proper co-processor does not exist in the system
  • If the appropriate co-processor is present but not enabled
  • If NEON/VFP (Vector Floating Point) access rights are not properly configured
  • When NEON/VFP executes the NEON/VFP instruction while NEON/VFP is stopped
  • Execution of a privileged instruction in non-privileged mode

SVC (Supervisor Call) Exception

When you invoke an instruction to run in a privileged mode state from user mode, you use the SVC instruction to raise an SVC exception; when you use an SVC exception, you use the SVC instruction and the SVC number, but the range of the SVC number setting depends on the instruction format.

【The Thumb instruction contains an 8-bit SVC number】

【The Arm instruction contains a 24-bit SVC number】

There is no register to indicate the SVC number.The SVC exception handler must obtain the address of the SVC instruction and the SVC number according to the instruction format.

prefetch abort exception

When an instruction fetch failure occurs, a prefetch abort exception is raised; the IFSR (Instruction Fault Status Register) can be used to check the cause of the occurrence, and the IFAR (Instruction Fault Address Register) can be used to check the address that occurred.

【IFSR】

The IFSR holds status information about the last instruction fault; it is defined as a 32-bit register and can be accessed in privileged mode only. If the security extension is implemented, it is a bank register.

【register format】

BitsNameContent
12ExtExternal Abort Type
It can be used to provide an implementation-defined classification for external data aborts.
For non-external aborts, this bit always returns 0.
10,3:0FSfault-task bit
Arm Architecture Reference Manual Armv7-A and Armv7-R Edition　See “VMSA (Virtual Memory System Architecture) VMSAv7 IFSR Encoding.

【Register Access Instructions】

MRC p15,0,<Rt>,c5,c0,1 ; Reading IFSR.
MCR p15,0,<Rt>,c5,c0,1 ; Writing to IFSR.

Data Abort Exception

When a data access failure occurs and a data boat exception occurs, the DFSR (Data Fault Status Register) shows the cause of the occurrence.

【DFSR】

The DFSR holds status information about the last data fault; it is defined as a 32-bit register and can be accessed in privileged mode only. If the security extension is implemented, it is a bank register.

【register format】

BitsNameContent
12ExtExternal abort type
It can be used to provide an implementation-defined classification for external data aborts. For non-external aborts, this bit always returns 0.
11WnRAccess in the event of an abort
0: Abort caused by read access.
1: Abort caused by write access.
10,3:0FSFault Startus BitsArm Architecture Reference Manual Armv7-A and Armv7-R Edition　See VMSA (Virtual Memory System Architecture) VMSAv7 DFSR Encoding.
7:4DomainFault Addressed Domains

【Register Access Instructions】

MRC p15,0,<Rt>,c5,c0,0 ;  DFSRの読み込み。
MCR p15,0,<Rt>,c5,c0,0 ;  DFSRへの書き込み。

interruption

IRQ interrupt

When the I bit of the current program status register (cpsr) is set to 0 and the IRQ pin is enabled, the IRQ interrupt exception is generated.

How to control IRQ interrupts using the compiler built-in function

Arm compiler allows you to enable or disable IRQ interrupts in the built-in functions.

function nameOperation Overview
int __disable_irq(void) Disables the IRQ interrupt and returns the previous IRQ interrupt setting.
void __disable_irq(void)Disables IRQ interrupts.
void __enable_irq(void)Allows IRQ interrupts.

Example IRQ interrupt control program that can work on all architectures

This is not an atomic operation (*1) as it performs cpsr read, modify and write operations.

I_Bit EQU 0x80 ; Defines the IRQ bit.

enable_irq(void); IRQ interrupt is enabled.
; Function type: void enable_irq(void)
enable_irq
    MSR r0,CPSR ; Read cpsr into the r0 register.
    BIC r0,#I_Bit ; Set I bit to 0.
    MRS CPSR_c,r0 ; Write r0 register to cpsr.
    BX lr ; Return function.

BX lr ; Return function; disable IRQ interrupt.
Function type: void disable_irq(void)
disable_irq
    MSR r0,CPSR ; Read cpsr into the r0 register.
    ORR r0,#I_Bit ; Set the I bit to 1.
    MRS CPSR_c,r0 ; Write r0 register to cpsr.
    BX lr ; Return function.

(*1) Atomic means that when multiple operations are combined, they become one operation in terms of the rest of the system.

An example of IRQ interrupt control program that can run on Arm v6 or later

.
The Cortex-A series can use the IRQ interrupt enable/disable instructions available in Arm v6 and later.

enable_irq(void); IRQ interrupt is enabled.
; Function type: void enable_irq(void)
enable_irq
    CPSIE I ; Allow IRQ interrupts.
    BX lr ; Return function.
BX lr ; Disable IRQ interrupt.
Function type: void disable_irq(void)
disable_irq
    CPSID I ; Disable IRQ interrupts.
    BX lr ; Return function.

FIQ interrupt

When the F bit of cpsr is zero and the FIQ pin is enabled, the FIQ interrupt exception is raised.

How to control FIQ interrupts using the compiler built-in function

.
Arm compiler allows you to enable or disable FIQ interrupts in the built-in functions.

.

.

.

function nameOperation Overview
int __disable_fiq(void) Disables the FIQ interrupt and returns the previous FIQ interrupt setting.
void __disable_fiq(void) Disables the FIQ interrupt.
void __enable_fiq(void)Allows FIQ interrupts.

Example FIQ interrupt control program that can work on all architectures

.
This is not an atomic operation, as it performs cpsr read, modify and light operations.

F_Bit EQU 0x40 ; Define FIQ bit.

Enable FIQ interrupt.
; Function type: void enable_fiq(void)
enable_fiq
    MSR r0,CPSR ; Read cpsr into the r0 register.
    BIC r0,#F_bit ; Set F bit to 0.
    MRS CPSR_c,r0 ; Write r0 register to cpsr.
    BX lr ; Return function.

BX lr ; Return function; disable FIQ interrupt.
Function model: void disable_fiq(void)
disable_fiq
    MSR r0,CPSR ; Read cpsr into the r0 register.
    ORR r0,#F_bit ; Set F bit to 1.
    MRS CPSR_c,r0 ; Write r0 register to cpsr.
    BX lr ; Return the function.

Example FIQ interrupt control program that can work on all architectures

.
This is not an atomic operation, as it performs cpsr read, modify and light operations.

F_Bit EQU 0x40 ; Define FIQ bit.

Enable FIQ interrupt.
; Function type: void enable_fiq(void)
enable_fiq
    MSR r0,CPSR ; Read cpsr into the r0 register.
    BIC r0,#F_bit ; Set F bit to 0.
    MRS CPSR_c,r0 ; Write r0 register to cpsr.
    BX lr ; Return function.

BX lr ; Return function; disable FIQ interrupt.
Function model: void disable_fiq(void)
disable_fiq
    MSR r0,CPSR ; Read cpsr into the r0 register.
    ORR r0,#F_bit ; Set F bit to 1.
    MRS CPSR_c,r0 ; Write r0 register to cpsr.
    BX lr ; Return the function.


Example of IRQ interrupt handler description


When writing interrupt handlers in the Cortex-A series, it is common to write them in assembly language. The following procedure is used to create an interrupt handler.

    

  1. Save the registers r0 to r3, r12, r14(lr) to the stack. 
    2. 
Call the 
  2. irq_handler() function and execute the interrupt process. 
    3. .

  3. Return r3, r12, r14(lr) registers from r0 to r3, r12, r14(lr) from the stack. 
    4. 

  4. R14(lr) is corrected and returned. 
    5. 



IRQ interrupt handler example


IRQ_Handler
    PUSH {r0-r3,r12,lr} ; Save the register to the stack.
    BL irq_handler ; Call an interrupt handler.
    POP {r0-r3,r12,lr} ; Return a register from the stack.
    SUBS pc,lr,#4 ; Correct return address and return from exception handling.

Why do you save the r0 to r3, r12, and r14(lr) registers to the stack? AAPCS (Procedure on Arm Architecture) (call standard)" provides a hint.
  • When using each of the registers from
  • r4 to r11, evacuate to the stack and do not evacuate in the interrupt handler.
  • When using the r0 to r3 and r12 registers, doesn't save to the stack, the interrupt handler will save to the stack.
  • The r14(lr) register is used in the call to the irq_handler() function, so it is saved on the stack.
  
 
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