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PMU (Performance Monitoring Unit)

投稿日 2015年6月30日 APS 0

　

PMU Overview

Until now, it has been common to use the trace (program execution history) function of debugging tools to measure execution time for program performance evaluation. To solve this problem, the Cortex-A series includes a PMU that consists of a cycle counter that measures the number of cycles and an event counter that measures specific events.

The PMU’s cycle and event counters are both 32-bit counters with a single cycle counter and an event counter with a single point. Depending on the processor core, the Cortex-A9 has six points. For cycle and event counter overflows, the overflow interrupt can be used for longer measurements.

(*1) When an overflow interrupt for the cycle counter and event counter is used, the interrupt affects program execution.

How to use PMU

This section explains how to measure the execution time of a function using the PMU cycle counter.

  1. Since access to the registers associated with the PMU is prohibited in user mode, set the PMUSERENR (user enable register) to user mode access permission in privileged mode.
  2. The PMU is in the inactive state at reset and is set up to be operational.
  3. Since the measurement time is approximately 4.2 seconds at 1GHz operating clock, consider setting the clock to 1/64th of a frequency or using an overflow interrupt if necessary.
  4. Appends the volatile modifier to the variable that stores the cycle counter value.
  5. Allows or resets the cycle counter and stores the number of start cycles in a variable.
  6. Perform the process for the measurement target.
  7. Stores the number of end cycles in a variable.
  8. Get the number of execution cycles from the start and end cycle variables using a debug tool or other tool.

【Sample program for cycle counting】

volatile unsigned long start_pmu_counter;   // Start cycle
volatile unsigned long end_pmu_counter;     // End cycle
…
    pmu_start();                            // Activate the PMU
    pmu_enable_counter();                   // Allow the cycle counter
    pmu_reset_counter();                    // Reset the cycle counter
    start_pmu_counter = pmu_read_counter(); // Get the number of cycles to start
    func1();                                // Execute the process of performing the measurement
    end_pmu_counter = pmu_read_counter();   // Get the number of end cycles
…

PMU control function

The control functions to be used for measurement with the PMU are as follows

NoProcessing detailsfunction name
1 Set up the PMU in the operational state.void pmu_start(void)
2 Resets the cycle counter.void pmu_reset_counter(void)
3 Resets the event counter.void pmu_reset_evnt_counter(void)
4 Set the cycle counter to active.void pmu_enable_counter(void)
5 Sets the event counter 0 to active.void pmu_enable_event0(void)
6 Sets the event to 0 in the event counter.void pmu_set_event0(int event)
7 Reads a cycle counter measurement.unsigned long pmu_read_counter(void)
8 Reads the event counter 0 measurement.unsigned long pmu_read_event0(void)

【Example of PMU Control Program】

; Set up the PMU in an operational state
; void pmu_start(void)
pmu_start
    MRC    p15, 0, r0, c9, c12, 0 ; Reads the PMCR (Performance Monitor Control Register)
    ORR    r0, r0, #0x1           ; Set the E bit (operational setting).
    MCR    p15, 0, r0, c9, c12, 0 ; Light the PMCR.
    BX     lr
; Reset the cycle counter
; void pmu_reset_counter(void)
pmu_reset_counter
    MRC    p15, 0, r0, c9, c12, 0 ; Leading the PMCR
    ORR    r0, r0, #0x4           ; Set the C bit (reset the cycle counter).
    MCR    p15, 0, r0, c9, c12, 0 ; Light the PMCR.
    BX    lr
; Reset the event counter
; void pmu_reset_evnt_counter(void)
pmu_reset_evnt_counter
    MRC    p15, 0, r0, c9, c12, 0 ; Leading the PMCR
    ORR    r0, r0, #0x2           ; Set the P bit (reset the event counter).
    MCR    p15, 0, r0, c9, c12, 0 ; Light the PMCR.
    BX    lr
; Set the cycle counter to active.
; void pmu_enable_counter(void)
pmu_enable_counter
    MRC    p15, 0, r0, c9, c12, 1 ; Reads the PMCNTENSET (count enable set register)
    ORR    r0, r0, #0x80000000    ; Set the C bit (permission setting).
    MCR    p15, 0, r0, c9, c12, 1 ; Light the PMCNTENSET
    BX     lr
; Event counter 0 is set to active.
; void pmu_enable_event0(void)
pmu_enable_event0
    MRC    p15, 0, r0, c9, c12, 1 ; Leading the PMCNTENSET
    ORR    r0, r0, #0x1           ; Set the P0 bit (permission setting).
    MCR    p15, 0, r0, c9, c12, 1 ; Light up PMCNTENSET
    BX    lr
; Set the event counter to 0.
; void pmu_set_event0(int event)
pmu_set_event0
    MOV    r1, #0x0               ; Select event counter 0
    MCR    p15, 0, r1, c9, c12, 5 ; write to PMSELR (event counter selection register).
    MCR    p15, 0, r0, c9, c13, 1 ; write to PMXEVTYPER (event selection register).
    BX    lr
; Read cycle counter measurements
; unsigned long pmu_read_counter(void)
pmu_read_counter
    MRC    p15, 0, r0, c9, c13, 0 ; Read the PMCCNTR (cycle count register)
    BX    lr
;  Reads the event counter 0 measurement.
; unsigned long pmu_read_event0(void)
pmu_read_event0
    MOV    r0, #0x0               ; Select event counter 0
    MCR    p15, 0, r0, c9, c12, 5 ; Light on PMSELR
    MRC    p15, 0, r0, c9, c13, 2 ; Lead the PMXEVCNTR 
    BX    lr

List of registers

This section describes the registers for using the PMU with Cortex-A9. For detailed register contents, please refer to the Arm Architecture Reference Manual Armv7-A and See Armv7-R Edition.

Performance Monitor Control Register (PMCR)

.

This register activates or deactivates the PMU and resets the clock and event counters.

NameFeatures
N
Number of event counters available (Cortex-A9 has 6 points).
D Sets the frequency dividing ratio of the measurement clock.
0: Does not divide the clock. 1: Divides the clock by 1/64.
1: Divides the clock by 1/64.		.
C Reset the cycle counter.
0: no operation. 1: reset the cycle counter.
1: Reset the cycle counter.
P Resets the event counter.
0: No action is taken.
1: Reset all event counters.
E Set the operation of the PMU.
0: The PMU is in the non-operational state.
1: the PMU is in the active state.

PMCNTENSET (Count Enable Set Register)

This register sets the cycle or event counter to active.

  • 0: Cycle counter is inactive (write disabled).
  • 1: Cycle counter deactivated.

NameFeatures
C Set the operation of the cycle counter.
P5 Set up operation of

 Set up event counter 5.
P4 Set up operation of

event counter 4.
P3 Set up operation of

event counter 3.
P2 Set up the operation of

event counter 2.
P1Set event counter 1 working.
P0 Set event counter 0 activity.

PMCNTENCLR (Count Enable Clear Register)

This register sets the cycle or event counter to inactivity.

  • 0: Cycle counter is inactive (write disabled).
  • 1: Cycle counter deactivated.

NameFeatures
C Set cycle counter deactivation.
P5Set deactivation of the

event counter 5.
P4Set deactivation of

event counter 4.
P3Set deactivation of

event counter 3.
P2Deactivate event counter 2.
P1Set deactivation of event counter 1.
P0Set deactivation of the

event counter 0.

PMSELR (Event Counter Select Register)

This register is used to select the event counter to be used. When an event counter number (0 to 5 for the Cortex-A9) is set in this register, the PMXEVTYPER (event type selection register) or the PMXEVCNTR (event count register) can be written to or read from this register.

PMCCNTR (Cycle Count Register)

This register counts the processor’s clock cycles.

PMXEVTYPER (Event Type Selection Register)

This register selects the events to be counted using the event counter, which includes events defined for the Cortex-A/R series and processor-specific events, defined as event numbers. to 0x3F, with processor-specific event numbers of 0x40 to 0xFF.

【Typical Event Type Setting Values】
Event TypeFeature Summary
0x09This counts all exceptions obtained.
0x0A Counts a return instruction from an exception.
0x70Number of main execution unit instructions (approximate value)
0x71Number of instructions of the second execution unit (approximate value)
0x72Number of load/store instructions (approximate value)
0x74Number of NONE instructions (approximate value)

PMXEVCNTR (Event Count Register)

This register allows you to read the event counter value selected by PMSELR.

PMUSERENR (User Enable Register)

This register sets user mode access to the PMU.

  • In privileged mode, PMUSERENR is a read/write register.
  • In user mode, PMUSERENR is read-only.

NameFeatures
EN Configures PMU access to user mode.
0: User mode access to the PMU is not possible.
1: User mode access to the PMU is possible.

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