Compilation of the Linux kernel
The Linux kernel is configured to select the required features and then compiled. The main body of the kernel is zImage and the per-board configuration that the kernel loads is dtb.
※Some also published in the 4th Download the source $ git clone https://github.com/altera-opensource/linux-socfpga.git Environment Variable Settings $ . /opt/poky/2.1.1/environment-setup-cortexa8hf-neon-poky-linux-gnueabi SoC FPGAs for $ cd linux-socfpga.git $ make socfpga_defconfig Fine-tuning the features of the kernel $ make nconfig Compilation $ make zImage dtbs Copy the built image to SD card $ cp arch/arm/boot/zImage The mount point of the SD card FAT partition
There are several ways to select a feature, but in this article we will introduce nconfig. This time we’ll show you nconfig, which is configured by manipulating the UI on the console.
For example, to set up to use the debugger, go through the menu in the following order to enable the item
Kernel hacking ---> Compile-time checks and compiler options ---> [*] Compile the kernel with debug info
If there is a feature you don’t understand, you can see more information by pressing F2.
How to debug the Linux kernel
Watch the video at the beginning for more details!
The command presented in the video is here. View the process list:. Linux on the menu -> Display Processes View of the source running: of the command B:: list /core 0 B:: list /core 1 Register View: The Register of the command B:: register /core 0 B:: register /core 1 Register View: The Register Symbols display and retrieval:. Show -> Symbols -> Browse Break Point Settings: Break Point Setting Breaks in the menu -> List
The search is done from the text box at the top of the window.
The break is double-clicked to the right of the line number. It will be set and marked in red.
Cyclone V SoC-equipped board by Altera
The Altera SoC integrates an Arm-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces with a customizable FPGA fabric on a high-bandwidth interconnector backbone. The hard IP includes PCI Express Gen2, multi-memory ports, ECC, memory protection and high-speed serial transceivers, combining features of low performance and power consumption with programmable logic flexibility. It significantly reduces the system board size, which previously consisted of a CPU and FPGA. In this course, the DE0-Nano-SoC Kit/Atlas-SoC Kit from Terasic will be used.
Japan Altera Corporation
TRACE32 made by Lauterbach
The world’s most used hardware-assisted debugger, TRACE32, which supports more than 70 processor architectures, not to mention Arm as well as Nios II. The multicore support of SMP systems allows you to control multiple cores simultaneously and to use the reference core as a Debugging can proceed seamlessly while switching between them. Another feature is the standard OS recognition function that supports the debugging of Linux and other SMP-compatible operating systems. This allows you to smoothly debug a program running in user space without worrying about which core the task to be debugged is assigned to.
Nippon Rotabacher K.K.
Embedded Linux Deployment / Development Support Services
Embedded Linux brings new value to your equipment development.
Fujitsu Computer Technologies
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