Write Buffer, Barrier Instructions

write buffer
Need to control the write buffer
Barrier Command

write buffer

What is a light buffer

Generally, the bus clock is slow relative to the processor core clock, and as the processor core waits for the processor core to complete writing to memory, execution is slowed down. To overcome this problem, a write buffer (FIFO memory) is provided between the processor core and the bus interface unit to reduce the processor core’s execution speed. Because the processor core can write to the write buffer at the core clock speed, it does not wait to write to the bus interface unit. If there is no space in the write buffer, the processor core remains in the wait state until it is free.

Three types of instructions are called barrier instructions: the DMB (data memory barrier) instruction and the DSB (data synchronization barrier) instruction, which control the write buffer, and the ISB (instruction synchronization barrier) instruction, which flushes (discards) the pipeline.

Please refer to the Technical Reference Manual for the number of steps in the write buffer. In case of Cortex-A9, there are four 64-bit slots with data binding function.

Need to control the write buffer

The Arm processor performs memory accesses according to the memory type and access order (see Part 10). If you want to observe the access order between peripherals located in device memory and memory located in normal memory, you need to control the write buffer by DMB or DSB instructions. In addition, combined control of the cache (Clean / Invalidate) must be considered.

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2014.12.30

【List of relationships between memory types and cache/write buffers】
No	Memory Type	Cache	write buffer
1	Normal Memory	◯	◯
2	Device Memory	×	◯
3	Strongly Ordered Memory	×	×

Barrier Command

Action of the Barrier Instruction

Barrier instructions in assembly language

Operation limitation is omitted because it is not recommended.

No	Instruction Name	Assembly Instructions
1	Data Synchronization Barrier	`DSB`
2	Data Memory Barrier	`DMB`
3	Instruction Synchronization Barrier	`ISB`

Barrier instructions in C/C++ language

The Arm compiler is “Arm C Language Extensions 2.0defines three different barrier instructions that can be used by the C/C++ language. accs (arguments) are deprecated, so the default value of 15 is set.

No	Instruction Name	function name
1	Data Synchronization Barrier	`void __dsb(unsigned int accs)`
2	Data Memory Barrier	`void __dmb(unsigned int accs)`
3	Instruction Synchronization Barrier	`void __isb(unsigned int accs)`

Action of the DMB instruction

All memory accesses that existed before the DMB instruction are guaranteed to be accessed and completed first. The “ADD r0,r1,r2” instructions, except for the memory access instructions, are executed.

【Sample Program】

Action of the DSB instruction

The processor is placed in a wait state so that no subsequent instructions are executed until all memory accesses that existed before the DSB instruction have been completed. The memory access instruction and the “ADD r0,r1,r2” instruction will not be executed either.

【Sample Program】

Action of the ISB instruction

Ensures that the Arm processor pipeline is flushed (discarded). The pipeline stage instructions are discarded and the instructions are re-fetched from the memory system.

Standby Mode and Barrier Instruction Case Study

This section describes the case where an interruption from a peripheral causes the processor to return from standby mode and continue processing. If you want to put the processor into standby mode by using the WFI(*1) built-in function after a peripheral access, use the DSB built-in function.

(*1) If the processor executes a WFI instruction, execution is held in abeyance. For more information, see the Arm Architecture Reference Manual Armv7-A and Armv7-R Edition See .

Operation description

Writing “0x00000003” to the STATUS register, which is memory-mapped at 0x40000000 causes the COUNT register to be subtracted at the input clock edge and an interrupt is generated at 0x0. The STATUS/COUNT register is placed in the device.

Program Description

Writes a set value to the STATUS/COUNT register to generate an interrupt.
The write to the STATUS/COUNT register executes the next instruction when the write buffer is finished.
There is no guarantee that the contents of the write buffer will be written to the STATUS/COUNT register as the Arm processor core enters standby mode upon execution of the WFI built-in function.
The order of access to “normal memory” and “device memory” is not guaranteed, so it waits for the DSB built-in function to finish writing.

【プログラム例】

#define STATUS (*(volatile unsigned long *)0x40000000) // status register
#define COUNT  (*(volatile unsigned long *)0x40000004) // counter register

    COUNT   = 10000;                      // Stops the processor for a period of time.
    STATUS = 0x00000003;                  // Operation and interrupt permission
    __wfi();                              // Processor cores to standby.

【Example of a modified program】

#define STATUS (*(volatile unsigned long *)0x1C010000) // status register
#define COUNT  (*(volatile unsigned long *)0x1C010004) // counter register

    COUNT   = 10000;                      // Stops the processor for a period of time.
    STATUS = 0x00000003;                  // Operation and interrupt permission
    __dsb(15);                            // Complete all memory accesses.
    __wfi();                              // Processor cores to standby.

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