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Linux Profiles
JTAG Profiler
Embedded Trace FIFO (ETF)
Embedded Trace Router (ETR)

Linux Profiles

# Linux provides tools to harvest profiles and traces, such as perf and ftrace. While this is a software implementation and therefore easy to try out, it does incur measurement overhead. The profiles and traces presented here using TRACE32 can be performed in a production-like environment using the functions of the Arm core, which allows us to obtain highly accurate information.

First, we will download and compile rt-tests, the benchmark program we will use.

# Download the source
$ git clone http://git.kernel.org/pub/scm/linux/kernel/git/clrkwllms/rt-tests.git

# Environment Variable Settings
$ . /opt/poky/2.1.1/environment-setup-cortexa8hf-neon-poky-linux-gnueabi

# Compilation
$ cd rt-tests
$ make

# Copy hackbench to SD card for this use
$ cp hackbench SD card rootfs partition mount point/appropriate directory

JTAG Profiler

You can take a profile using TRACE32, which samples the values of the PC registers of the JTAG communication, generating a high accuracy profile with no overhead.

The command presented in the video is here.

Performance of the menu -> Performance Measurement Settings

Click the Arm radio button and start measuring.

You can see the profile results on a per-core basis with the following command
B:: perf.list /core 0
B:: perf.list /core 1

Profiler Setup Screen

Profile results (core 0)

Profile Results (Core 1)

Embedded Trace FIFO (ETF)

The Embedded Trace FIFO (ETF) stores trace data in memory within the SoC. It has a small capacity (32KB for the Cyclone V SoC), but it does not require the wiring of an Embedded Trace Macrocell (ETM) on the board, and JTAG alone provides a trace with no overhead.

ETF Settings
aps_etf.cmm

Onchip.DISable
Onchip.TraceCONNECT ETF1
Trace.METHOD Onchip
Onchip.Init
Onchip

ETF Settings Screen

【Trace results】Click the List button and you will see the trace results.

【Trace results】Clicking on the overview takes you to the C language view.

【Chart view of the trace results】
Menu Trace -> Chart Display -> Click on a symbol and the transition of the symbol is charted.

【Chart view of the trace results】
You can click or scroll the mouse wheel to zoom in.

Embedded Trace Router (ETR)

The Embedded Trace Router (ETR) stores trace data in the DDR on the board; there is an overhead on the bus as DDR accesses occur, but no ETM wiring is required and large traces are possible with JTAG alone. The area for storing the trace data must be configured on both the kernel and debugger side. In this case, the last 4MB of addresses 0x0-0x3FFF_FFFF, where DDR is mapped, is set as the area for trace data.

Kernel-side settings:
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts

        memory {
                name = "memory";
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
        };
        ↓ ↓ ↓ ↓
        memory {
                name = "memory";
                device_type = "memory";
                reg = <0x0 0x3fc00000>; /* 1GB - 4MB for ETR */
        };

# Compilation of dtb
$ make dtbs

# A copy of dtb
$ cp arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb SDカードのFATパーティションのマウントポイント

t32/demo/arm/etc/embedded_trace_router/etr_utility.cmm you will see the following dialog

To AXIBase0x3fc00000
Size 0x400000

The Set & Press the Init button.

The trace settings screen will appear automatically.

You can get the same traces as ETFs in large quantities.

Menu Traces -> Saving trace data allows you to save trace data to your PC, and reading trace data allows you to read the saved data.

The large amount of trace data can be used as evidence for review, as you may find something you want to analyze later, or it can be converted to an image file.

Cyclone V SoC-equipped board by Altera

The Altera SoC integrates an Arm-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces with a customizable FPGA fabric on a high-bandwidth interconnector backbone. The hard IP includes PCI Express Gen2, multi-memory ports, ECC, memory protection and high-speed serial transceivers, combining features of low performance and power consumption with programmable logic flexibility. It significantly reduces the system board size, which previously consisted of a CPU and FPGA. In this course, the DE0-Nano-SoC Kit/Atlas-SoC Kit from Terasic will be used.
Japan Altera Corporation

TRACE32 made by Lauterbach

The world’s most used hardware-assisted debugger, TRACE32, which supports more than 70 processor architectures, not to mention Arm as well as Nios II. The multicore support of SMP systems allows you to control multiple cores simultaneously and to use the reference core as a Debugging can proceed seamlessly while switching between them. Another feature is the standard OS recognition function that supports the debugging of Linux and other SMP-compatible operating systems. This allows you to smoothly debug a program running in user space without worrying about which core the task to be debugged is assigned to.
Nippon Rotabacher K.K.