MMU (Memory Management Unit)

Setting up the MMU

When using the Arm processor, set the memory type (see Part 10) for the memory area. Set normal memory to enable caching for the program and data areas, and set device memory or strong order memory for the peripheral areas. When using an Arm processor with MMU, memory type (normal memory, device memory, or strong order memory), cache and access rights are set in the MMU, so you need to understand the settings and use the MMU. You have to.

Outline of MMU operation

Address translation from virtual to physical addresses uses the MMU and a translation look-ahead buffer (TLB). The address translation is performed automatically by referring to the translation table in the table walk unit and also caches the TLB. You can set the memory type, cache attributes, and buffer attributes in the conversion table.

The conversion table consists of a first level table and a second level table. The first level table converts a virtual address to a physical address in units of 16 Mbytes and 1 Mbytes, and the second level table allows you to convert a virtual address to a physical address in finer units of 64 Kbytes and 4 Kbytes. The unit of conversion from virtual address to physical address is called page size, with 16M bytes being called a “super section,” 1M bytes being called a “section,” 64K bytes being called a “large page,” and 4K bytes being called a “small page.

Virtual to physical address translation operation

The MMU performs address translation according to the following procedure.

1. From the virtual address [31:20] bit, refer to the corresponding one-word (4-byte) first level descriptor in the first level table.
2. First level descriptor settings to determine whether to seek a physical address or refer to a second level table.
3. When using the second-level table, the physical address is obtained from the virtual address [19:12] bits by referring to the corresponding one-word (4-byte) second-level descriptor in the second-level table.
4. The first level table is 16K bytes in size in physical memory space and placed on a 16K byte boundary, and the second level table is 1K bytes in size in physical memory space and placed on a 1K byte boundary.

Conversion table and page size

The first address of the first level table is set to either TTBR0 (conversion table base register 0) or TTBT1 (conversion table base register 1), so two types of first level tables can be used. To use one type of first level table, use TTBR0.

(*1) Supersection support is optional.

Formality of the first-level descriptor

The first level table is set up with a one-word (4-byte) first level descriptor. In the [1:0] bit, select “Fault”, “Page Table”, “Section”, or “Super Section”. In the case of “Page Table”, set the first address of the second level table on a 1K byte boundary, and set it to the physical address [31:20] in the case of “Section” or [31:24] in the physical address in the case of “Super Section”. For other settings, see Level Descriptor Settings below.

第2レベル記述子の形式

The second bell table is set up with a one-word (4-byte) second bell descriptor. The [1:0] bits select “Fault”, “Large Page”, or “Small Page”. Set it to the physical address [31:16] for ‘large page’ and [31:12] for ‘small page’. For other settings, see Level Descriptor Settings below.

About the level descriptor setting

Describes the various settings to be made for the first-level and second-level descriptors.

Memory types and cache settings list

Sets the memory type, cache settings and sharing settings. Shared settings may not be possible depending on the memory type settings. if TEX[2]=1. set the cache to internal and external attributes separately.

Settings at TEX[2]=1

The internal and external attributes of the cache can be configured in the following format (Internal attribute: L1 cache, Internal attribute: L2 cache)

Setting up access rights

With AP[2:0], you can set up access rights for each page size. When you want to change multiple access attributes, you can use the “Domain” in the first level table to change the access privileges efficiently. See How to Use Domains below for details.

Other settings

Set the

How to use the domain

The domain ([8:5] bits) setting for the first level descriptor “Page Table” and “Section” is selected D0 from D15 in the DACR (Domain Access Control Register). The “Super Section” has no domain setting, so D0 is selected. The access settings are made per page size, but if you want to change the access permissions for multiple pages, you must perform TLB maintenance at the same time as changing multiple first-level descriptors. you can ignore the permissions setting for the conversion table by rewriting the domain number setting in the DACR.

【DACR】

Address translation using a table

Address translation using the first level table

A “section” using the first level table describes the operation of translating a virtual address to a physical address. The first level table is located at 0x000F_0000 and converts the virtual address 0x0010_0000 to a physical address.

1. Use the [31:20] bits of the virtual address to find the offset address of the first level table.
2. The first level table stores the first level descriptor for every 1M byte of virtual address, so the address of the first level table is obtained using the following formula.
   Address offset = virtual address [31:20] bits x 4 =0x001 x 4 =0x004
   table address
   = 1st level table address + address offset
   = 0x000F_0000+0x004 = 0x000F_0004
3. Read the first level descriptor at 0x000F_0004, and the [31:20] bit of the first level descriptor becomes the [31:20] bit of the physical address, and the [19:0] bit of the virtual address becomes the [19:0] bit of the physical address.

Section address translation example

The following is an example of how to set up a virtual address to physical address conversion in “sections” using the first level table. Place the three non-contiguous virtual address regions into a contiguous physical address space.

When setting up the first level table, the [31:20] bit of the virtual address references the table, the [31:20] bit of the table becomes the [31:20] bit of the physical address, and the [19:0] bit of the physical address becomes the [19:0] bit of the virtual address. For example, to convert the 0x400n_nnnn address, the offset of the first level table would be 0x400×4=0x1000, and the [31:20] bit of the table would be set to 0x002. If you access the 0x400n_nnnn address of the virtual address, you will access the 0x002n_nnnn address of the physical address.

Address Translation Using Second Level Tables

Here’s what happens when you perform a physical address conversion from a virtual address in a “small page” using the first and second level tables. The first level table is placed from address 0x000F_0000 and converts the virtual address 0x0020_0000 to a physical address.

1. Use the [31:20] bits of the virtual address to find the offset address of the first level table.
2. Since the first level table stores the first level descriptor for every 1M byte of virtual address, the address of the first level table is calculated using the following formula.
   Address offset = virtual address [31:20]bits x 4 = 0x002 x 4 = 0x008
   table address
   = 1st level table address + address offset
   = 0x000F_0000+0x008 = 0x000F_0008
3. Read the first level descriptor at 0x000F_0008, and the [31:10] bit of the first level descriptor is the first address of the second level table.
4. Bits [19:12] of the virtual address indicate the virtual address space access location in 4K bytes.
   Address offset = virtual address [19:12]bits x 4 = 0x00 x 4 = 0x000
5. Read the second level descriptor of the second level table, where the [31:12] bit of the second level descriptor becomes the [31:12] bit of the physical address and the [11:0] bit of the virtual address becomes the [11:0] bit of the physical address.

An example of small page address configuration

Using the first and second level tables, here’s an example of how to set up a virtual address to physical address conversion in “small pages A 32K-byte space from virtual address 0x4000_0000 is placed in 4K-byte increments starting with physical addresses 0x0010_0000 and 0x0020_0000 at the beginning.

.

Refer to the first level table with the [31:20] bit of the virtual address to find the first address of the second level table. Refer to the second level table with the [19:12] bits of the virtual address, and the [31:12] of the table becomes the [31:12] of the physical address, and the [11:0] bits of the physical address become the [11:0] bits of the virtual address. For example, to convert the address 0x4000_0nnn, the offset of the first level table would be 0x400×4=0x1000, and the first address of the second level table set to the [31:10] bit of the table would be found. The offset of the second level table will be 0x00×4=0x00 and set the second level table to 0x00100 in bit [31:12] of the table. If you access the virtual address 0x4000_0nnn, you access the physical address 0x0010_0nnn.

Sample Program

Here is a sample program for the first level table with “Section” selected. Place it as virtual address = physical address.

Sample program for creating the first level table

This is a sample program that creates the construction of the first level table in the RAM area. The program sets the area from 0x0 to 1M bytes as normal memory/internal cache is write back/no write allocations/no external cache is allowed. The other regions are set up for Strong Order Memory and the first level table is placed from 0x0010_0000. Set the domain to reference D16.

LEVEL1_BASE_ADDR EQU 0x00100000 ; First address of the first level table
VECTOR_BASE_ADDR EQU 0x00000000 ; Vector table top address

;
; TTBCR (Table Conversion Base Control Register) / TTBR0
;
  MOV r0,#0x0 ; Initial value of TTBCR 0x0
  MCR p15,0,r0,r0,c2,c0,2 ; Writing the TTBCR
  LDR r0,=LEVEL1_BASE_ADDR ; Set the first level table address.
  MOV r1,#0x48 ; Initialize TTBR0.
                               ; TTBR0.IRGN[6.0]=01:Normal memory
                               ; internal write back write allocation cacheable
                               ; TTBR0.S[1]=0: Do not share
                               ; TTBR0.RGN[4:3]=01: Normal memory
                               ; External write-back, write-allocation and cacheable
  ORR r0,r0,r1 ; Set the value of TTBR0.
  MCR p15,0,r0,r0,c2,c0,0 ; Writing of TTBR0
;
; Creation of the first level table.
;
  LDR r0,=LEVEL1_BASE_ADDR ; Set the first level table address.
  LDR r1,=0xfff ; Initialize the loop counter.
  LDR r2,=0x00000de2 ; Set the initial setting for the table
init_ttb_1
  ORR r3,r2,r1,LSL#20 ; Set the base address.
  STR r3,[r0,r1,LSL#2]; 1st descriptor write
  SUBS r1,r1,#1 ; Set the loop counter to -1
  BPL init_ttb_1 ; finished creating the conversion table?
;
; Change the first descriptor of the vector area
;
  LDR r1,=VECTOR_BASE_ADDR ; Set the first address of the vector.
  LSR r1,#20 ; Set the address on a 1 Mbyte boundary.
  ORR r3,r2,r1,LSL#20 ; Find the initial value of the table.
  ORR r3,r3,#0x0c ; normal memory internal cache enablement
  ORR r3,r3,#0x1000 ; disable external cache
  STR r3,[r0,r1,LSL#2] ; Set table entry.

Initializing Domains

The domain settings are set to “client” for all settings from D0 to D15. The domain settings for the first level descriptor (setting a range of 5 to 8 bits) refer to the DACR. The “client” setting follows the access setting for the first level descriptor.

;==================================================
; All client settings in the domain access control register
;==================================================
  LDR  r0,=0x55555555         ; Client Settings
  MCR  p15,0,r0,c3,c0,0       ; Writing to DACR

Setting up the MMU

The MMU is set to be inactive at reset, so enable all settings after the end of the day. After confirming that the first level table settings (4096 first level descriptors)/TTBCR settings/TTBR0/TTBR1/DACR settings are appropriate, set the M bit of SCTLR to enable.

;
; Set the MMU up and running.
;
  MRC  p15,0,r0,c1,c0,0     ; Read SCTLR
  ORR  r0,r0,#0x1           ; Set MMU to active (SCTLR.M[0])
  MCR  p15,0,r0,c1,c0,0     ; Writing to SCTLR

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